Integrated Systems Designer Dev

Selected responsibilities:

• Designing schematics, in-depth analysis, and simulation of analog, digital, and mixed CMOS integrated circuits.
• Performing topography of CMOS integrated circuits.
• Developing and programming the test and startup environment using, among others, FPGA circuits.
• Parallel creation of gateware for Xilinx FPGA and Verilog firmware for ASIC for mutual communication.
• Preparing progress reports.

Expectations:

• Higher education in a relevant field.
• Very good knowledge of Verilog and VHDL languages.
• Very good knowledge of the Vivado tool.
• Experience working with MGT blocks, DDR.
• Experience with version control systems.
• Experience in HDL implementation in ASIC using Cadence tools is a plus.
• Familiarity with FPGA tools Misoc/Migen/ARIQ is welcome.
• Knowledge of the Cadence environment.
• Knowledge of verification tools LVS, DRC, ERC.
• Knowledge of Genus Synthesis Solution, Innovus Implementation System, Voltus IC Power Integrity Solution.”